1. Field of the Invention
The present invention relates to a method for forming a metal layer, and more particularly, to a method for forming a metal layer using atomic layer deposition.
2. Description of the Related Art
As the integration of a semiconductor device increases, the design rule is reduced. Thus, the aspect ratio of a contact hole becomes higher, but the junction depth becomes shallower. The junction depth directly depends on a short channel effect of a MOS transistor. That is, a MOS transistor appropriate for a highly-integrated semiconductor device requires a short channel length, and the depth of a source/drain region, i.e., the junction depth, must be shallow to improve the characteristics of the MOS transistor having the short channel. An interconnection technology for connecting the shallow junction to a metal interconnection requires a barrier metal layer. This prevents the metal interconnection from penetrating into the shallow junction, i.e., prevents a junction spiking phenomenon. A titanium nitride (TiN) layer is widely used for the barrier metal layer, and an ohmic layer, e.g., a titanium silicide layer, is interposed between the barrier metal layer and the junction. The titanium silicide layer has a melting point of 1540.degree. C., a resistivity of 13.about.16 .mu.U-cm and a barrier height of 0.6eV with respect to an N-type impurity layer, and is widely used for the ohmic layer of the interconnection. The titanium silicide layer used for the ohmic layer is formed by forming a titanium layer on the junction, i.e., a silicon substrate (impurity layer) doped with an impurity, and then annealing to react the titanium layer with the silicon substrate.
As described above, in a conventional method for forming the metal interconnection, an interdielectric layer is formed on an impurity layer, and the interdielectric layer is patterned to form a contact hole exposing a predetermined region of the impurity layer. The ohmic layer, the barrier metal layer and the metal interconnection are formed in sequence on the entire surface of the resultant structure where the contact hole is formed. Here, the ohmic layer can be obtained by forming a titanium layer on the exposed impurity layer and annealing the titanium layer, or forming the titanium silicide layer directly on the impurity layer. The titanium suicide layer must be formed at a temperature low enough to avoid damage to the impurity layer. Thus, there has been proposed a method for forming a titanium silicide layer using plasma-enhanced chemical vapor deposition (PECVD), in "Plasma Enhanced CVD of Blanket TiSi.sub.2 on Oxide Patterned Wafer" by J. Lee et al., J. Electrochem. Soc., vol. 139, No. 4 1992, pp. 1159-1165, and in "Material characterization of plasma-enhanced CVD titanium silicide", by Alan E. Morgan et al., J. Vac. Sci. Technol. B4(3), 1986, pp. 723-731. However, when the titanium silicide layer is formed on the contact hole having a high aspect ratio in a highly-integrated semiconductor device, the titanium silicide layer shows poor step coverage due to the plasma characteristics. Meanwhile, a method for forming a titanium silicide layer using a low pressure CVD (LPCVD) process at 600 C. or higher has been proposed by V. llderem et al. and G. J. Reynolds et al. (see "Optimized Deposition Parameters for Low pressure CVD titanium silicide", J. Electrochem. Soc., 1988, pp. 2590-2596 and "Selective titanium disilicide by Low Pressure CVD", J. Appl. Phys. 65(8), 1989, pp. 3212-3218). However, when the titanium silicide layer is formed at 600.degree. C. or higher, silicon consumption of the impurity layer contacting the titanium layer is increased, deteriorating junction leakage current characteristics. Thus, it is difficult to adapt the LPCVD titanium silicide layer to be suitable for a highly-integrated semiconductor device requiring a shallow junction.